In complementary metal oxide semiconductor (CMOS) technology a P channel insulated gate field effect transistor IGFET is in series with an N channel IGFET between a positive and a negative power supply terminal so that one of the two transistors is always off in a static condition to prevent current from flowing between the two power supply terminals in the static condition. Being able to detect a transistor transistor logic (TTL) output while keeping one of the P and N channel IGFETs off over the TTL output range is desirable in order to minimize power consumption. To conserve power is a typical reason for using CMOS. Because a TTL output can be as low as 2.0 volts for a logic "1", there is difficulty ensuring the P channel IGFET is off while contemporaneously ensuring the N channel IGFET is on.
When the TTL signal is at 2.0 volts, the P channel IGFET conventionally has its threshold voltage exceeded by a greater magnitude than does the N channel IGFET whereas the desire is for the P channel IGFET to actually be off. The logic "0" presents a substantially less severe problem because the range for a TTL logic "0" is only 0.0 to 0.8 volts. The N channel IGFET may have a sufficiently large threshold voltage that even at a 0.8 volt input the N channel IGFET will be off. Even if it is on, it will be biased on by only several tenths of a volt. This will, however, cause some waste of power because there will be some current flowing in the static condition.